1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device having a redundancy structure.
2. Description of the Background Art
In order to repair defective memory cells to improve the yield, a conventional semiconductor memory device includes redundant memory cells to substitute for the defective memory cell.
In recent years, the demand for a large bus width to improve the data transfer speed is great. There is the tendency of a larger data line width and a relatively smaller column address. Particularly in a dynamic random access memory (DRAM embedded with a logic circuit directed to system-on-chip, there is the demand of increasing the bus width from 32 bits to 256 bits and reducing the column address from 256 bits to 16 bits.
In a conventional semiconductor memory device, repair of a defective memory cell was carried out by exchanging the bit lines through a column address. When the column address is small, a high repair rate cannot be achieved unless a relatively large amount of redundant memory cells are prepared.
To this end, the method of arranging a redundant memory cell and a redundant data line connected to that redundant memory cell to exchange the defective data line with a redundant data line is being employed.
In a logic-embedded DRAM, the method is employed of providing a large internal bus width and selecting a required bus width using a column address at the connection to an external source so as to accommodate a variety of bus widths.
An example of a conventional semiconductor memory device 5000 with a redundancy structure will be described with reference to FIG. 64. Semiconductor memory device 5000 includes a memory cell array 500 with a plurality of memory cells arranged in a matrix, a plurality of normal data line pairs 501 connected to memory cells via a sense amplifier, a redundant data line pair 502, a row decoder 510 decoding an input row address to carry out selection in a row direction, a column address decoder 511 decoding an input column address for output, a shift redundancy circuit 512 including position information of a defective data line, an IO select circuit 503 selecting a data line, a read amplifierxe2x80xa2write driver unit 504, and an IO shift circuit 505.
IO select circuit 503 selects a data line pair to be used according to the output of column address decoder 511. Referring to FIG. 65, IO select circuit 503 is formed of a plurality of switches. Half of normal data line pairs LIO(0), LIO(0), . . . are connected to read amplifierxe2x80xa2write driver unit 504. Redundant data line pair SLIO(0), /SLIO(0) or SLIO(1), SLIO(1) is connected to read amplifierxe2x80xa2write driver unit 504.
Read amplifierxe2x80xa2write driver unit 504 includes a plurality of read amplifierxe2x80xa2write drivers RW (read amplifier R, write driver W). By read amplifierxe2x80xa2write driver unit 504, the data of the selected data line pair are transmitted to internal data lines DB(0), and redundant internal data line SDB, or the data of internal data lines DB(0), and redundant internal data line SDB are transmitted to the selected data line pair.
In IO shift circuit 505, the connection between the internal data line and the data input/output pin (external data line) is shifted to remove a defective data line according to the data line shift method, as shown in FIG. 66. More specifically, the defective data line is replaced with an adjacent data line. The data line used for replacement is further replaced with an adjacent data line. By repeating replacement between adjacent data lines, the last data line is replaced with the redundant data line. As a result, data lines other than the defective data line are connected to data input/output pins (external data line) DQ(0)-DQ(n).
Thus, data of a selected memory cell is output to an external source. In a write operation, data is written into a selected memory cell through an opposite path.
According to the structure of the conventional semiconductor memory device, the pass through the switch circuit to switch the data lines and the data line switch circuit for redundancy replacement is inevitable, causing delay in data transfer.
In view of the foregoing, an object of the present invention is to provide a semiconductor memory device capable of high speed data transfer in a semiconductor memory device having a redundancy structure.
According to an aspect of the present invention, a semiconductor memory device includes a memory cell array with a plurality of memory cells arranged in a matrix, a plurality of data lines with a redundant data line and a normal data line to read out data or write in data from/to the memory cell array, a plurality of external data lines to transfer data with an external source, and a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with a plurality of external data lines and a shift operation of shifting the connection of a data line to be coupled to a plurality of external data lines according to an external address and data line information related to a defective data line in the normal data lines.
Preferably, the plurality of data lines are divided into a plurality of blocks. The data line switch circuit includes a decoder decoding an external address and data line information, and a plurality of select circuits arranged between a plurality of blocks and the plurality of external data lines respectively. Each of the plurality of select circuits carries out a select operation and a shift operation simultaneously according to the output of the decoder. Each of the plurality of select circuits shares some of the data lines with an adjacent select circuit.
Each of the plurality of select circuits includes a plurality of transfer gates provided between a corresponding data line and a corresponding external data line to be open/closed according to the output of the decoder.
According to the semiconductor memory device having a redundant data line of the present aspect, execution of the data line shift redundancy scheme and selection of a data line specified by an address can be carried out simultaneously. Therefore, high speed data transfer is allowed.
According to another aspect of the present invention, a semiconductor memory device includes a memory cell array with a plurality of memory cells arranged in a matrix, a plurality of data lines with a redundant data line and a normal data line to read out or write in data from or to the memory cell array, and a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with a plurality of external data lines according to an external address and a replace operation of replacing a defective data line in the data line to be coupled with a redundant data line according to data line information related to a defective data line.
Preferably, the plurality of normal data lines are divided into a plurality of blocks. The data line switch circuit includes a decoder decoding an external address and data line information, and a plurality of select circuits. Each of the plurality of select circuits carries out simultaneously a select operation and a replace operation.
Particularly, each of the plurality of select circuits includes a plurality of transfer gates that are open/closed according to the output of the decoder, provided between a redundant data line and corresponding normal data line and a corresponding external data line.
According to the semiconductor memory device having a redundant data line of the present aspect, data transfer can be carried out at high speed since the data line replace operation and the data line select operation are carried out simultaneously.
According to a further aspect of the present invention, a semiconductor memory device includes a memory cell array with a plurality of memory cells arranged in a matrix, a plurality of data lines with a redundant data line and a normal data line to read out or write in data from or into the memory cell array, and a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with an external data line to be used according to a bus width and a shift operation of shifting connection between the external data line to be used and the data line to be coupled according to data line information related to a defective data line in the normal data line.
Preferably, each of the plurality of data lines and plurality of external data lines is divided into a plurality of blocks. The plurality of blocks share some data lines with an adjacent block. The data line switch circuit includes a plurality of switch circuits arranged corresponding to the plurality of blocks, respectively. Each of the plurality of switch circuits belongs to any of the status of a mode switching the connection between a corresponding data line and a corresponding external data line according to a bus width, a mode of substituting the defective data line with a common data line, and shifting connection between a corresponding external data line and a corresponding data line according to the bus width, and a mode of shifting connection between a corresponding data line and a corresponding external data line according to the bus width.
Particularly, each of the plurality of switch circuits includes m nodes, a first gate selectively switching the connection between the m nodes and m external data lines according to the bus width, a second gate rendering a defective data line and m nodes nonconnected according to the bus width and data line information, and a third gate selectively connecting a common data line with one of the m nodes according to the bus width and the data line information.
According to the semiconductor memory device of the present aspect, the data line select circuit and the redundant replacement circuit are shared in common. The shift redundancy scheme is employed in combination on a block-by-block basis to switch the bus width. Therefore, data can be transferred at high speed.
According to still another aspect of the present invention, a semiconductor memory device includes a memory cell array with the plurality of memory cells arranged in a matrix, a plurality of data lines with first and second redundant data lines and a plurality of normal data lines to read out or write in data from/to the memory cell array, a plurality of external data lines provided corresponding to the plurality of normal data lines, respectively, to transfer data with an external source, and a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with an external data line to be used according to a bus width and a shift operation of shifting the connection of a data line to be coupled to the external data line to be used according to data line information related to a defective data line in the plurality of data lines.
Preferably, the first and second redundant data lines are respectively arranged at an outer side of the plurality of normal data lines. The plurality of data lines are arranged in the order of the first redundant data line, respective plurality of normal data lines, and the second redundant data line. The plurality of external data lines are divided into a plurality of blocks, each block corresponding to n external data lines. The plurality of data lines are divided for every (n+2) data lines in order so that two normal data lines are shared between adjacent blocks, corresponding to the plurality of blocks, respectively. The data line switch circuit includes a plurality of switch circuits arranged corresponding to the plurality of blocks, respectively. Each of the plurality of switch circuits belongs to any one of first to sixth modes, i.e., the first mode with no defective data line in a corresponding block, switching the connection between a corresponding normal data line and a corresponding external data line according to the bus width; the second mode without a defective data line in the corresponding block, shifting the connection between a corresponding external data line and a corresponding data line according to the bus width to the first redundant data line side; the third mode without a defective data line in the corresponding block, shifting the connection between a corresponding external data line and a corresponding data line according to the bus width to the second redundant data line side; the fourth mode with one defective data line in the corresponding block, replacing the one defective data line using one of the data line from corresponding (n+2) data lines shared with an adjacent block at the first redundant data line side and the first redundant data line, and shifting the connection between the corresponding external data line and corresponding data line according to the bus width; the fifth mode with one defective data line in the corresponding block, replacing the one defective data line using one of the data line from the corresponding (n+2) data lines shared with an adjacent block at the second redundant data line side and the second redundant data line, and shifting the connection between the corresponding external data line and corresponding data line according to the bus width; and the sixth mode with two defective data lines in the corresponding block, replacing two defective data lines using one of the data line shared with an adjacent block at the first redundant data line side and the first redundant data line, and using one of the data line shared with an adjacent block at the second redundant data line side and the second redundant data line from corresponding (n+2) data lines, and shifting the connection between the corresponding external data line and corresponding data line according to the bus width.
Particularly, each of the plurality of switch circuits includes n nodes, a switch unit selectively switching the connection between n nodes and n external data lines according to the bus width, and a select unit rendering the defective data line and n nodes nonconnected, and connecting n of the corresponding (n+2) data lines with the n nodes, based on the bus width, the data line information, and the mode of the corresponding block.
Preferably, each of the plurality of switch circuits is forced to one of the second and third modes, switchable from an external source in a test mode.
Preferably, one of the plurality of switch circuits corresponding to the first redundant data line and one of the plurality of switch circuits corresponding to the second redundant data line are forced to the fourth and fifth modes, respectively, in a test mode.
Preferably, each of the plurality of switch circuits is forced to the first mode in a test mode.
According to the above semiconductor memory device, the data line select circuit and the redundant replacement circuit are shared in common. In a semiconductor memory device of a multidata line structure and that can have the bus width switched by combining the shift redundancy scheme on a block-by-block basis, data can be transferred at high speed. Also, the redundancy efficiency can be improved since two defective data lines can be replaced at the same time.
Since the shift operation can be forced to be executed all the blocks according to the test mode signal, a test mode confirming the data line switch function at each switch circuit constituting the data line switch circuit can be set.
Also, the test mode of accessing simultaneously the two redundant data lines and confirming whether there is a defect corresponding to the redundant data lines can be set.
Since a test mode that allows access of respective data lines excluding the redundant data line, i.e., of the normal data lines from a predetermined external data line can be set even after the information related to the defective data line is programmed, internal defect analysis can be executed efficiently.
Preferably, the respective plurality of external data lines and plurality of normal data lines are divided into a plurality of blocks. The data line switch circuit includes a plurality of switch circuits arranged corresponding to the plurality of block, respectively. Each of the plurality of switch circuits corresponds to any one of the first to fourth modes; i.e. the first mode without a defective data line in a corresponding block, switching the connection between a corresponding normal data line and corresponding external data line according to the bus width; the second mode with one defective data line in the corresponding block, replacing the one defective data line by a shift operation using the first redundant data line; the third mode with one defective data line in the corresponding block, replacing the one defective data line by a shift operation using the second redundant data line; and the fourth mode with two defective data lines in the corresponding block, replacing the two defective data lines by a shift operation using the first and second redundant data lines.
Particularly, each of the plurality of switch circuits includes n nodes, a switch unit selectively switching the connection between the n nodes and n external data lines according to the bus width, and a select unit rendering the defective data line and the n nodes nonconnected, and connecting n data lines out of the corresponding n normal data lines and first and second redundant data lines with the n nodes based on the bus width, the data line information, and the mode to which the corresponding block belongs.
Preferably, two of the plurality of switch circuits are forced to the second and third modes, respectively, in a test mode.
According to such a semiconductor memory device, the data line select circuit and redundant replacement circuit are shared in common. In a semiconductor memory device of a multidata line structure and that can have the bus width switched by combining a shift redundancy scheme on a block-by-block basis, the redundancy efficiency can be improved since two defective data lines can be replaced at the same time. Furthermore, since a shift operation is executed only at the block with a defective data line, data line switching can be controlled relatively easily in the data line switch circuit. In comparison to the structure in which each data line is directly replaced with a redundant data line, the number of external data lines connected to the redundant data line can be suppressed. As a result, the parasitic capacitance of the internal redundant data line can be reduced to allow data transfer at high speed.
Since a test mode that allows direct access towards the redundant data line can be set, determination can be made whether there is a defect in the corresponding redundant data line or whether the data input/output speed is altered by using the redundant internal data line.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.